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Data Sheet August 1999
L8567 SLIC for People's Republic of China Applications
Features
s
Description
General
This electronic subscriber loop interface circuit (SLIC) is optimized for low cost and low power consumption while providing a full-feature set. Included in the feature set is quiet reverse battery. Quiet polarity reversal is possible because the ac path is uninterrupted during transmission. The dc loop current limit is user-adjustable via a single external resistor. The maximum battery voltage is specified as -65 V for long loop applications. The L8567 supports on-hook transmission. The total short loop off-hook power may be reduced by use of a lower-voltage auxiliary battery supply. If, when using the 32-pin PLCC, the user does not wish to supply an auxiliary battery, the component of the total short loop off-hook power that is dissipated on the L8567 SLIC is controlled by use of an external power resistor. With the 44-pin PLCC, a power resistor is not necessary. Included are both the loop closure and ring trip supervision functions. The loop closure threshold is fixed internally, which eliminates the need for an external precision resistor to set the threshold. To minimize noise at the supervision output, hysteresis is included on the loop closure function. The loop closure and ring trip outputs are multiplexed into a single NSTAT output. Also included is a thermal shutdown mechanism. If device temperature exceeds 165 C, as may be the case under an extended power cross fault, the SLIC will shut down (i.e., enter a high-impedance state) to provide protection against the fault. A logic output will indicate the SLIC is in thermal shutdown.
Low active power (typical 149 mW during on-hook transmission) Sleep state for low idle power (47 mW typical) Quiet tip/ring polarity reversal Distortion-free on-hook transmission -35 V to -65 V battery operation Convenient operating states: -- Forward active -- Polarity reversal active -- Sleep -- Forward disconnect Supervision functions: -- Fixed threshold off-hook detector with longitudinal rejection and hysteresis -- Ring trip detector -- Thermal shutdown indication Adjustable loop current limit Three driver outputs for relay driver LED driver output to indicate off-hook Latched parallel data interface Battery and +5 V required: -- Optional auxiliary lower voltage battery to reduce short loop power -40 C to +85 C operational temperature range User-selectable power management techniques Thermal protection 32-pin PLCC or 44-pin PLCC packaging
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L8567 SLIC for People's Republic of China Applications
Data Sheet August 1999
Table of Contents
Contents Page
Outline Diagrams.......................................................39 32-Pin PLCC ........................................................39 44-Pin PLCC ........................................................40 Ordering Information..................................................41
Features ......................................................................1 Description...................................................................1 General...................................................................1 Application for People's Republic of China ............4 Pin Information ............................................................6 Coding Information ......................................................9 Absolute Maximum Ratings.......................................11 Recommended Operating Conditions .......................11 Electrical Characteristics ...........................................12 Logic Interface .....................................................14 Ring Trip Requirements .......................................16 Test Configurations ...................................................17 RFI Rejection........................................................19 Functional Description ...............................................21 General.................................................................21 Use with T7507 Codec for Use in People's Republic of China ..............................................21 Chip Set Performance Specifications ........................22 Gain......................................................................22 Gain Flatness--In Band .......................................22 Gain Flatness--Out of Band--High Frequencies .......................................................22 Gain Flatness--Out of Band--Low Frequencies .......................................................22 Loss vs. Level Relative to Loss at -10 dBm Input at 1020 Hz ................................................23 Return Loss ..........................................................23 Hybrid Balance .....................................................23 Applications ...............................................................24 Design Considerations .........................................26 Characteristic Curves ...........................................27 Power Control.......................................................28 Power Control--Auxiliary Battery .........................29 Power Control--32-Pin PLCC with Power Control Resistor .................................................29 Power Considerations ..........................................30 Power Control--44-Pin PLCC Package ...............32 dc Characteristics ......................................................33 Loop Range..........................................................34 dc Applications ..........................................................34 On-Hook Transmission.........................................34 Supervision...........................................................35 Loop Closure ........................................................35 Ring Trip Detection...............................................36 Other Supervision Functions ................................36 Latched Parallel Data Interface ............................37 ac Design .............................................................38 First-Generation Codecs ......................................38 Second-Generation Codecs .................................38 Third-Generation Codecs .....................................38 T7507 Codec........................................................38 2
Figures
Page
Figure 1. Functional Diagram .....................................5 Figure 2. 32-Pin Diagram (PLCC Chip) ......................6 Figure 3. 44-Pin Diagram (PLCC Chip) ......................6 Figure 4. Ring Trip Circuits .......................................16 Figure 5. Timing Requirements ................................16 Figure 6. Basic Test Circuit ......................................17 Figure 7. Metallic PSRR ...........................................18 Figure 8. Longitudinal PSRR ....................................18 Figure 9. Longitudinal Balance .................................18 Figure 10. Longitudinal Impedance ..........................18 Figure 11. ac Gains ..................................................18 Figure 12. RFI Rejection Test Circuit .......................19 Figure 13. RFI Testing, Forward Battery, 600 Loop, No Capacitor, 1 Vrms .........20 Figure 14. RFI Testing, Forward Battery, 600 Loop, No Capacitor, 2 Vrms .........20 Figure 15. Termination Impedance ...........................22 Figure 16. Transmit and Receive Direction Frequency-Dependent Loss Relative to Gain at 3400 Hz ..................................22 Figure 17. Loss vs. Level ..........................................23 Figure 18. Return Loss .............................................23 Figure 19. Hybrid Balance ........................................23 Figure 20. Basic Loop Start Application Using T7507 Codec and L7583 Switch for 200 + (680 || 100 nF) Complex Termination and Hybrid Balance .............24 Figure 21. L8567 Typical VCC Power Supply Rejection .................................................27 Figure 22. L8567 Typical VBAT Power Supply Rejection .................................................27 Figure 23. L8567 Loop Current vs. Loop Voltage .....27 Figure 24. L8567 Loop/Battery Current (with Battery Switch) vs. Loop Resistance ...................27 Figure 25. Power Derating ........................................28 Figure 26. Tip/Ring Voltage Decrease .....................33 Figure 27. SLIC 2-Wire Output Stage .......................34 Figure 28. Ring Trip Equivalent Circuit and Equivalent Application .............................36 Figure 29. Simplified Control Scheme ......................37 Figure 30. Logic Output Latches .............................. 38
Lucent Technologies Inc.
Data Sheet August 1999
L8567 SLIC for People's Republic of China Applications
Table of Contents (continued)
Tables Page
Table 1. Pin Descriptions ........................................................................................................................................7 Table 2. Input State Coding ....................................................................................................................................9 Table 3. Supervision Coding .................................................................................................................................10 Table 4. Power Supply ..........................................................................................................................................12 Table 5. 2-Wire Port ...............................................................................................................................................13 Table 6. Analog Pin Characteristics .......................................................................................................................13 Table 7. ac Feed Characteristics ...........................................................................................................................14 Table 8. Logic Inputs (B0, B1, EN, RD1I, RD2I, and RD3I) and Outputs (NSTAT and NTSD) ............................14 Table 9. Drivers (RD1O, RD2O, and RD3O) .........................................................................................................15 Table 10. LED Driver (NLED) .................................................................................................................................15 Table 11. Timing Requirements (DI, EN, DO, and RD), CCLK = 2.048 MHz ........................................................16 Table 12. Gain ........................................................................................................................................................22 Table 13. Gain Flatness--In Band .........................................................................................................................22 Table 14. Gain Flatness--Out of Band--Low Frequencies ...................................................................................22 Table 15. Parts List for Loop Start Application .......................................................................................................25 Table 16. 200 + 680 || 0.1 F Design Parameters .........................................................................................26 Table 17. Power Connections ................................................................................................................................28 Table 18. RPWR = 2600 ......................................................................................................................................31 Table 19. RPWR = 2200 ......................................................................................................................................31 Table 20. RPWR = 1800 ......................................................................................................................................31 Table 21. RPWR = 4400 ......................................................................................................................................32 Table 22. RPWR = 2310 (RPWR = 2200 + 5%)................................................................................................ 32 Table 23. RPWR = 2090 (RPWR = 2200 - 5%)................................................................................................ 32 Table 24. Valid Data at NSTAT and NTSD ............................................................................................................38
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L8567 SLIC for People's Republic of China Applications
Data Sheet August 1999
output and is gated via the EN input. The other (NLED) can be used to drive an LED to indicate loop states. The NLED driver is an open collector output, so multiple outputs may be used to drive a single LED. NLED is not gated, so valid supervision data appears at NLED regardless of the state of EN. NLED can be used as an alternative, nongated, data control output. The L8567 is available in a 32-pin PLCC or 44-pin PLCC package.
Description (continued)
General (continued)
This device uses a latched parallel data input interface and a gated parallel output data interface. Level-sensitive data latches are used for state control inputs, and level-sensitive control gates are used for supervision outputs. Latch and gate control are through an ENABLE pin. When the ENABLE pin is high, input data is latched and the SLIC will not respond to changes at its logic input. When ENABLE is low, input control data will flow through the latch. Valid supervision data will appear at the NSTAT and NTSD outputs only when ENABLE is low. In this manner, the data input and data output of multiple SLICs can be serviced by a single control input or output. The L8567 is designed to be controlled/supervised using control/supervision outputs and inputs from the T7507 codec. Three relay drivers are also included. These drivers are meant to drive electromechanical relays (EMRs). State control of the relay drivers is via latched parallel data inputs. Like the B0/B1 and supervision data, control leads from the T7507 codec drive these inputs. The T7507 relay driver control outputs are meant to control the associated control input on all four of the L8567 SLICs associated with the T7507 codec. If an L7583 solid-state switch is used (instead of EMRs), the data control outputs from the T7507 codec will drive the latched state control inputs of the L7583 directly. Again, one data control output from the T7507 will drive the corresponding data input on four channels of the L7583. In the case of using the L7583, tie RD1I, RD2I, and RD3I relay driver control inputs of the L8567 to ground. Included are two supervision outputs. Both supervision outputs are the wire-OR of the loop closure and ring trip detectors. One (NSTAT) is used as a data control
Application for People's Republic of China
This SLIC may be used with any commercially available codec; however, when used with the Lucent Technologies Microelectronics Group T7507, the two devices form a complete line circuit optimized for requirements in the People's Republic of China. The ac interface between the two components is extremely simple, requiring only a single capacitor in the transmit direction and a short-circuit connection, using no external components, in the receive direction. The complex 200 + 680 || 100 nF termination and hybrid balance is digitally synthesized by the T7507 codec. Additionally, the tip/ring to PCM (transmit) gain is fixed and set digitally by the T7507 codec at 0 dB. The PCM to tip/ring (receive) gain is also digitally set by the T7507 codec and is programmable via a bit in the codec serial data control stream to either -3.5 dB or -7.0 dB. The control interfaces of the L8567 and T7507 are designed for compatibility with each other. Both the T7507 codec and L8567 SLIC require only battery and +5 V to operate. When both devices are used, no -5 V supply is required.
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Lucent Technologies Inc.
Data Sheet August 1999
L8567 SLIC for People's Republic of China Applications
Description (continued)
Application for People's Republic of China (continued)
BGND
AGND
VBAT1
VBAT2
CF1
POWER CONDITIONING & REFERENCE
IPROG
CURRENT LIMIT SET
CF2
VCC
RECTIFIER
3
DCOUT
PWR
+
VTX
- -
PT TIP/RING CURRENT SENSE A=1 TG
+ -
1 RCVN RCVP VDD DGND
+
PR A = -1
+
-
NSTAT
LED DRIVE
NLED
LOOP CLOSURE DETECTOR
LATCHES
+ -
NLC
RELAY DRIVE
RD1O
RTSP RTSN RING TRIP DETECTOR THERMAL SHUTDOWN SENSE
+ -
NRDET
LOGIC
RELAY DRIVE
RD2O
NTSD
RD3I RD2I RD1I B1 NTSD B0 NSTAT EN
RELAY DRIVE
RD3O
FROM L8567 1, 2, 3
TO L8567 1, 2, 3*
FROM T7507 CODEC
TO T7507 CODEC
12-2551.f (F)
* Relay driver controls routed to L8567 RD1I, RD2I, and RD3I pins when using EMR. If L7583 solid-state switch is used, driver control buses are routed directly to L7583 control inputs, and SLIC pins RD1I, RD2I, and RD3I are grounded.
Figure 1. Functional Diagram
Lucent Technologies Inc.
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L8567 SLIC for People's Republic of China Applications
Data Sheet August 1999
Pin Information
NSTAT 30 29 28 27 26 NTSD EN RCVP RCVN AGND VTX TG CF2 CF1 25 24 23 22 14 RTSN 15 PR 16 PT 17 VBAT1 18 BGND 19 VBAT2 20 PWR 21 RD3O RD1I RD2I RD3I B0 32 B1 31
4 RD2O RD1O NLED DGND VDD VCC IPROG DCOUT RTSP 5 6 7 8 9 10 11 12 13
3
2
1
32-PIN PLCC
12-2548.i (F)
Figure 2. 32-Pin Diagram (PLCC Chip)
NSTAT 41 RD3O RD1I RD2I RD3I NTSD 40 39 38 37 36 35 44-PIN PLCC 34 33 32 31 30 29 18 RTSP 19 RTSN 20 NC 21 PR 22 PT 23 VBAT1 24 BGND 25 VBAT2 26 NC 27 PWR 28 NC NC EN RCVP RCVN NC AGND VTX NC TG CF2 CF1
NC
NC 43
6 RD2O RD1O NLED DGND VDD NC VCC NC NC IPROG DCOUT 7 8 9 10 11 12 13 14 15 16 17
5
4
3
2
1
44
NC 42
B0
B1
5-5779 (F).a
Figure 3. 44-Pin Diagram (PLCC Chip) 6 Lucent Technologies Inc.
Data Sheet August 1999
L8567 SLIC for People's Republic of China Applications
Pin Information (continued)
Table 1. Pin Descriptions 44-Pin 2 32-Pin 1 Symbol RD3I Type Description I Relay Driver 3 Input. This latched logic input sets the state of the relay driver number 3. When using EMRs, the relay driver is controlled by this input via a data bus or independent data line. When using an L758X solid-state switch, the solid-state switch is controlled directly via the data bus or independent data line and the relay driver is unused; in this case, tie this logic input to ground. I Relay Driver 2 Input. This latched logic input sets the state of the relay driver number 2. When using EMRs, the relay driver is controlled by this input via a data bus or independent data line. When using an L758X solid-state switch, the solid-state switch is controlled directly via the data bus or independent data line and the relay driver is unused; in this case, tie this logic input to ground. Relay Driver 1 Input. This latched logic input sets the state of the relay driver number 1. When using EMRs, the relay driver is controlled by this input via a data bus or independent data line. When using an L758X solid-state switch, the solid-state switch is controlled directly via the data bus or independent data line and the relay driver is unused; in this case, tie this logic input to ground. Relay Driver 3 Output. Output to drive an EMR, controlled by RD3I. No Connect.
3
2
RD2I
4
3
RD1I
I
6 5, 12, 14, 15, 20, 26, 28, 32, 35, 39, 42, 43 7 8 9
4 --
RD3O NC
O --
5 6 7
RD2O RD1O NLED
O O O
Relay Driver 2 Output. Output to drive an EMR, controlled by RD2I. Relay Driver 1 Output. Output to drive an EMR, controlled by RD1I. NSTAT LED Driver. This output is equivalent to NSTAT, except this output has sufficient drive capability to drive an LED. This LED driver output is an open-collector output, so multiple outputs may be used to drive a single LED. This output may be used as an alternative logic output to the latched NSTAT output to indicate ring trip or loop supervision status. This output is valid regardless of the state of EN.
10 11 13 16 17 18 19
8 9 10 11 12 13 14
DGND VDD VCC IPROG DCOUT RTSP RTSN
PWR Digital Ground. PWR +5 V Digital Power Supply. PWR +5 V Analog Power Supply. I O I I Current-Limit Program Resistor. A resistor to DCOUT sets the dc current limit. dc Output Voltage. This output is a voltage that is directly proportional to the absolute value of the differential tip/ring current. Ring Trip Sense Positive. Connect this pin to the ring relay and to the ringer series through a high-value resistor. Ring Trip Sense Negative. Connect this pin to the ringing generator through a high-value resistor.
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L8567 SLIC for People's Republic of China Applications
Data Sheet August 1999
Pin Information (continued)
Table 1. Pin Descriptions (continued) 44-Pin 32-Pin Symbol Type 21 22 23 24 25 15 16 17 18 19 PR PT VBAT1 BGND VBAT2 I/O I/O Description Protected Ring. The output of the ring driver amplifier and input to loop sensing circuitry. Connect to loop through overcurrent series resistance.
Protected Tip. The output of the tip driver amplifier and input to loop sensing circuitry. Connect to loop through overcurrent series resistance. PWR Battery Supply. Most negative primary high-voltage power supply. PWR Battery Ground. Ground return for battery supply. PWR Auxiliary Battery Supply. Connect to the lower-voltage (magnitude) auxiliary battery supply. If a lower-voltage auxiliary battery is not used, connect directly to the primary high-voltage battery side. PWR Power Control. With a 32-pin PLCC, connect a lower-voltage auxiliary battery supply directly to PWR or connect a resistor from this node to high-voltage battery to control short-loop power dissipation. With a 44-pin PLCC, connect the higher-voltage battery directly to PWR. Please see the Power Control section of this data sheet for more information. -- Filter Capacitor 1. Connect a 0.47 F capacitor from this pin to CF2. -- I Filter Capacitor 2. Connect a 0.1 F capacitor from this pin to AGND. Transmit Gain. Noninverting input to internal AX transmit amplifier. Connect a 7.87 k resistor from this node to VTX to set internal SLIC transconductance to 39.75 V/A. Transconductance of 39.75 V/A is assumed for use with T7507 codec. Transmit ac Output Voltage. Output of SLIC transmit amplifier. This output is a voltage that is directly proportional to the differential tip/ring current. Connect a 7.87 k resistor from this node to TG to set internal SLIC transconductance to 39.75 . Receive ac Signal (Inverting). This high-impedance input controls the ac differential voltage on tip and ring. Receive ac Signal (Noninverting). This high-impedance input controls the ac differential voltage on tip and ring. Data Enable. Level-sensitive data latch control; when high, data at the B0, B1, and relay driver control inputs is latched. When low, the data latch is transparent and control signals will flow through the data latch to the SLIC control logic. NSTAT and NTSD supervision outputs are valid only when EN is low. Not Thermal Shutdown. This gated logic output indicates if the L8567 die temperature has exceeded the thermal shutdown temperature and the device has entered the thermal shutdown mode. Input EN needs to be low for valid data to appear at NTSD. The actual thermal shutdown is not affected by EN. Loop Detector Output/Ring Trip Output. This gated logic output is a wired-OR of the Not Loop Closure/Not Ring Trip detect outputs. When low, this logic output indicates that an off-hook condition exists or that ringing has been tripped. Input EN needs to be low for valid data to appear at NSTAT. State Control Input. This latched logic input, with B0, controls the state of the SLIC. State Control Input. This latched logic input, with B1, controls the state of the SLIC.
27
20
PWR
29 30 31
21 22 23
CF1 CF2 TG
33
24
VTX
O
34 36 37 38
25 26 27 28
AGND RCVN RCVP EN
PWR Analog Signal Ground. I I I
40
29
NTSD
O
41
30
NSTAT
O
44 1
31 32
B1 B0
I I
8
Lucent Technologies Inc.
Data Sheet August 1999
L8567 SLIC for People's Republic of China Applications
Coding Information
Table 2 shows the input state coding. Table 2. Input State Coding B0* 1 B1* 1 RD3I* RD2I* RD1I* State/Definition Powerup, Forward Battery. Normal talk and battery feed state. Pin PT X X X is positive with respect to PR. On-hook transmission is enabled. The ring trip and loop closure detectors are active. Powerup, Reverse Battery. Normal talk and battery feed state. Pin PR X X X is positive with respect to PT. On-hook transmission is enabled. The ring trip and loop closure detectors are active. Low-Power Scan. Except for off-hook supervision, all circuits are shut X X X down to conserve power. Pin PT is positive with respect to PR. Thermal shutdown is active. Note that the ring trip detector is not active during the low-power scan. To ensure that the ring trip detector is active during ringing, the L8567 SLIC must be put into the forward or reverse powerup state before applying power ringing to the loop. Disconnect. The tip and ring amplifiers are turned off and the SLIC goes X X X into a high-impedance (>100 k) state. The L8567 will reset into this state on powerup. Driver RD1 Output Is Active. Input pin RD1I is high. This will activate or 1 X X place the RD1 driver output into the on state. In the on state, the driver will supply up to 40 mA of current (at 0.6 V) to the coil of an EMR, thus activating the EMR. 0 X X Driver RD1 Output Is Not Active. Input pin RD1I is low. This will place the RD1 driver output into the off state. In the off state, the driver will not supply current to the coil of an EMR, thus deactivating the EMR. Driver RD2 Output Is Active. Input pin RD2I is high. This will activate or X 1 X place the RD2 driver output into the on state. In the on state, the driver will supply up to 40 mA of current (at 0.6 V) to the coil of an EMR, thus activating the EMR. X 0 X Driver RD2 Output Is Not Active. Input pin RD2I is low. This will place the RD2 driver output into the off state. In the off state, the driver will not supply current to the coil of an EMR, thus deactivating the EMR. Driver RD3 Output Is Active. Input pin RD3I is high. This will activate or X X 1 place the RD3 driver output into the on state. In the on state, the driver will supply up to 40 mA of current (at 0.6 V) to the coil of an EMR, thus activating the EMR. X X 0 Driver RD3 Output Is Not Active. Input pin RD3I is low. This will place the RD3 driver output into the off state. In the off state, the driver will not supply current to the coil of an EMR, thus deactivating the EMR.
1
0
0
1
0
0
X
X
X
X
X
X
X
X
X
X
X
X
* All logic inputs are latched. The data latch is controlled by pin EN. The EN latch control is level sensitive. When EN is high, the input data latches are active; that is, data at the B0, B1, RD1I, RD2I, and RD3I inputs are latched. The latched data will control the state of the SLIC and drivers so that the SLIC and drivers will not respond to changes at the logic inputs while the level at EN is high. When EN is low, the input latch is not active; therefore, data at the logic inputs will flow through the latch and immediately determine the state of the SLIC and drivers. If using an L758X solid-state switch, the switch is controlled directly from the T7507 codec; thus the relay drivers in the L8567 SLIC cannot be used. If the relay drivers are not used, force them into the lowest power (not active) state by connecting RD1I, RD2I, and RD3I to ground.
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L8567 SLIC for People's Republic of China Applications
Data Sheet August 1999
Coding Information (continued)
Table 3 gives the output coding. Table 3. Supervision Coding Output NSTAT* 0 State Off-Hook or Ring Trip. dc current greater than the typical 11 mA loop current threshold is flowing in the subscriber loop, or the ring trip comparator has detected a dc voltage greater than the ring trip threshold. This indicates that dc current is flowing in the loop with the ring relay set in the power ring state. The presence of dc current in the power ring state implies that the handset is off-hook, or that a ring trip condition exists. This is a latched output. EN must be low for data on this output to be valid. On-Hook or Not Ring Trip. dc current less than the difference of the off-hook current threshold and loop current hysteresis is flowing, or the loop is in the power ringing state and the handset is on-hook--no dc current has been detected. This is a latched output. EN must be low for data on this output to be valid. The SLIC die temperature has exceeded the thermal shutdown temperature threshold, and the SLIC is forced into the equivalent of the disconnect state, regardless of the state of the B0 and B1 logic inputs. There is a hysteresis in the shutdown circuit, and the device will remain in thermal shutdown until the die temperature drops below the hysteresis threshold. This is a latched output. EN must be low for data on this output to be valid. The SLIC die temperature has not exceeded the thermal shutdown temperature threshold, and the SLIC state is set per B0 and B1 logic. This is a latched output. EN must be low for data on this output to be valid. Identical to the off-hook or ring trip state of output NSTAT. In this state, NLED can supply 10 mA at 1.0 V, which is sufficient to drive an LED. This output is an open collector output, so multiple NLED outputs from different devices can be used to drive a common LED. This output is not latched, so it has valid data regardless of the state of EN. NLED can be used as an alternative to the latched NSTAT output. Identical to the on-hook or not ring trip state of the pin NSTAT.
1
NTSD* 0
1
NLED 0
1
* Data outputs NSTAT and NTSD are gated. In order to drive the NSTAT or NTSD outputs low, both the internal detector (i.e., an off-hook or thermal shutdown condition, respectively, exists) and pin EN must be low. This output is not latched; data is valid regardless of the state of EN. It can be used to drive an LED or as an alternative unlatched ring trip/off-hook detector.
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Lucent Technologies Inc.
Data Sheet August 1999
L8567 SLIC for People's Republic of China Applications
Absolute Maximum Ratings (TA = 25 C)
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Parameter +5 V Power Supply +5 V Digital Supply Battery (talking) Supplies* Logic Input Voltage Analog Input Voltage Maximum Junction Temperature Storage Temperature Range Relative Humidity Range Ground Potential Difference (BGND to AGND) Symbol VCC VDD VBAT1, VBAT2 -- -- TJ Tstg RH -- Min -- -- -- -0.5 -7.0 -- -40 5 -- Typ -- -- -- -- -- -- -- -- -- Max 7.0 7.0 -70 7.0 7.0 165 125 95 3 Unit V V V V V C C % V
* Use of an auxiliary battery, VBAT2, whose magnitude is equal to the primary battery VBAT1 but does not exceed the absolute maximum rating, will not damage the chip. However, in a 32-pin PLCC, it will drive the L8567 into thermal shutdown under short-loop conditions. Use a power resistor to node PWR. Note: The IC can be damaged unless all ground connections are applied before, and removed after, all other connections. Furthermore, when powering the device, the user must guarantee that no external potential creates a voltage on any pin of the device that exceeds the device ratings. Some of the known examples of conditions that cause such potentials during powerup are 1) an inductor connected to tip and ring can force an overvoltage on VBAT through the protection devices if the VBAT connection chatters, and 2) inductance in the VBAT lead could resonate with the VBAT filter capacitor to cause a destructive overvoltage.
Recommended Operating Conditions
Parameter Ambient Temperature VCC Supply Voltage VDD Supply Voltage VBAT1 Supply Voltage VBAT2 Auxiliary Battery Supply Voltage dc Loop Current-limit Programming Range On- and Off-hook 2-wire Signal Level Min -40 4.75 4.75 -65 -35 15 -- Typ -- 5.0 5.0 -48 -24 40 3.17 Max 85 5.25 5.25 -35 -15 45 -- Unit C V V V V mA dBm
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L8567 SLIC for People's Republic of China Applications
Data Sheet August 1999
Electrical Characteristics
Minimum and maximum values are testing requirements in the temperature range of 25 C to 85 C and battery range of -35 V to -65 V. These minimum and maximum values are guaranteed to -40 C based on component simulations and design verification of samples, but devices are not tested to -40 C in production. The test circuit shown in Figure 6 is used unless otherwise noted. Positive currents flow into the device. Typical values are characteristics of the device design at 25 C based on engineering evaluations and are not part of the test requirements. Supply values used for typical characterization are VCC = VDD = 5.0 V, VBAT1 = -48 V, VBAT2 = -25.5 V. Table 4. Power Supply Parameter Power Supply Rejection 500 Hz to 3 kHz (See Figures 6 and 7.) 1: VCC (1 kHz) VBAT (500 Hz--3 kHz) Thermal Protection Shutdown (TTSD)1 Thermal Resistance, Junction to Ambient (JA) (still air)1: 32-pin PLCC 44-pin PLCC Power Supply--Powerup, No Loop Current with On-hook Transmission, Relay Drivers Off, dc Supplies at Typical Values, Use VBAT1 and VBAT2: ICC + IDD IBAT1 (VBAT1 = -48 V) IBAT2 (VBAT2 = -24 V) Quiescent Active Power Dissipation Power Supply--Low-power Scan, Forward Battery, No Loop Current, Relay Drivers Off, Use VBAT1 and VBAT2: ICC + IDD IBAT1 (VBAT1 = -48 V) IBAT2 (VBAT2 = -24 V) Quiescent Active Power Dissipation Power Supply--Powerup, No Loop Current with On-hook Transmission, Relay Drivers Off, dc Supplies at Typical Values, Use VBAT1 Only: ICC + IDD IBAT (VBAT1 = -48 V) Quiescent Active Power Dissipation2 Power Supply--Low-power Scan, Forward Battery, No Loop Current, Relay Drivers Off: ICC + IDD IBAT (VBAT1 = -48 V) Power Dissipation2 Min Typ Max Unit
35 45 -- -- --
-- -- 165 60 47
-- -- -- -- --
dB dB C C/W C/W
-- -- -- --
6.0 2.25 0.45 149
6.6 2.7 0.54 180
mA mA mA mW
-- -- -- --
4.0 0.61 0.0 47
4.5 0.78 0.0 60
mA mA mA mW
-- -- --
6.0 2.7 160
6.6 3.46 199
mA mA mW
-- -- --
4.0 0.61 47
4.5 0.78 60
mA mA mW
1. This parameter is not tested in production. It is guaranteed by design and device characterization. 2. This is the total power drawn from the power supplies. If a power resistor is not used, the total power is dissipated by the SLIC through the package. If a power resistor is used, the power is shared by the resistor and the SLIC.
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Lucent Technologies Inc.
Data Sheet August 1999
L8567 SLIC for People's Republic of China Applications
Electrical Characteristics (continued)
Table 5. 2-Wire Port Parameter Tip or Ring Drive Current = dc + Longitudinal + Signal Currents Signal Current1 Longitudinal Current Capability per Wire1, 2 dc Loop Current Limit3: RLOOP = 100 Programmability Range Accuracy (18 mA < ILIM < 45 mA) Powerup Open-loop Voltage Levels: Common-mode Voltage Differential Voltage Disconnect State: PT Resistance (VBAT < VPT < 0 V) PR Resistance (VBAT < VPR < 0 V) dc Feed Resistance (for ILOOP below current limit) Loop Resistance Range (3.17 dBm overload into 200 + 680 || 0.1 F): ILOOP = 18 mA at VBAT = -48 V Longitudinal to Metallic Balance--IEEE Std. 455 (See Figure 9.)5: 50 Hz to 300 Hz 300 Hz to 600 Hz 600 Hz to 3400 Hz Metallic to Longitudinal Balance: 1 kHz to 3 kHz
4
Min 65 10 8.5 -- 15 --
Typ -- -- 15 ILIM -- --
Max -- -- -- -- 45 15
Unit mA mArms mArms mA mA % V V M M
-- VBAT/2 -- |VBAT + 7.8| |VBAT + 7.1| |VBAT + 6.4| -- -- -- 1 1 110 -- -- --
1800
--
--
38 48 52 38
-- -- -- --
-- -- -- --
dB dB dB dB
1. This parameter is not tested in production. It is guaranteed by design and device characterization. 2. The longitudinal current is independent of dc loop current. 3. Current-limit ILIM is programmed by a resistor, RPROG, from pin IPROG to AGND. RPROG (k) = 1.59 ILIM (mA). 4. IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc. 5. Longitudinal balance of circuit card will depend on loop series resistance matching.
Table 6. Analog Pin Characteristics Parameter Differential PT/PR Current Sense (DCOUT) Gain (PT/PR to DCOUT): Forward Battery Reverse Battery Loop Closure Detector Threshold (on-hook to off-hook at VBAT1 = - 48 V) Loop Closure Detector Hysteresis: Variation Ring Trip Comparator: Input Offset Voltage RCVN, RCVP: Input Impedance Gain RCVP to PT/PR Gain RCVN to PT/PR Min Typ Max Unit
-- -- 9 -- -- -- -- -- --
-119 119 11 2 0.5 10 100 2 -2
-- -- 13 -- -- -- -- -- --
V/A V/A mA mA mA mV k -- --
Lucent Technologies Inc.
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L8567 SLIC for People's Republic of China Applications
Data Sheet August 1999
Electrical Characteristics (continued)
Transmit direction is tip/ring to 4-wire. Receive direction is 4-wire to tip/ring. Table 7. ac Feed Characteristics Parameter Total Harmonic Distortion--200 Hz to 4 kHz : Off-hook On-hook Transmit Gain, f = 1020 Hz (See Figure 11.); PT/PR to VTX Transmit Gain Receive Gain, f = 1020 Hz (See Figure 11.); RCVP/RCVN to PT/PR Receive Gain 2-wire Idle-channel Noise (200 + 680 Psophometric1 C-message 3 kHz Flat1 Transmit Idle-channel Noise: Psophometric1 C-message 3 kHz Flat1
1
Min -- -- 38.56 1.94
Typ -- -- 39.75 2
Max 0.3 1.0 40.94 2.06
Unit % % V/A --
|| 0.1 F termination):
-- -- -- -- -- -- -- -- -- -- -- -- -77 12 20 -77 12 20 dBmp dBrnC dBrn dBmp dBrnC dBrn
1. This parameter is not tested in production. It is guaranteed by design and device characterization.
Logic Interface
Table 8. Logic Inputs (B0, B1, EN, RD1I, RD2I, and RD3I) and Outputs (NSTAT and NTSD) Parameter1 High-level Input Voltage Low-level Input Voltage Input Bias Current (high and low) High-level Output Voltage (IOUT = -100 A) Low-level Output Voltage (IOUT = 180 A) Output Short-circuit Current (VOUT = VDD) Output Load Capacitance
2
Symbol VIH VIL IIN VOH VOL IOSS COL
Min 2.4 0 -- VDD - 1.5 0 1 0
Max VDDD 0.8 50 VDD 0.4 35 50
Unit V V A V V mA pF
1. Unless otherwise specified, all logic voltages are referenced to DGND. 2. This parameter is not tested in production. It is guaranteed by design and device characterization.
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Lucent Technologies Inc.
Data Sheet August 1999
L8567 SLIC for People's Republic of China Applications
(continued)
Electrical Characteristics
Logic Interface (continued)
Table 9. Drivers (RD1O, RD2O, and RD3O)1 Parameter2 Off-state Output Current (VOUT = VDD) On-state Output Voltage (IOUT = 40 mA) On-state Output Voltage (IOUT = 20 mA) Clamp Diode Reverse Current (VOUT = 0) Clamp Diode On Voltage (IOUT = 80 mA) Turn-on Time3 Turn-off Time3 Symbol IOFF VON VON IR VOC tON tOFF Min -- 0 0 -- VCC + 0.5 -- -- Max 200 0.60 0.40 10 VCC + 3.0 10 10 Unit A V V A V s s
1. The relay drivers operate using the VDD supply. When VDD is first applied to the device, the relay drivers will power up and remain in the off state until the SLIC is configured via the data interface. 2. Unless otherwise specified, all logic voltages are referenced to DGND. 3. This parameter is not tested in production. It is guaranteed by design and device characterization.
Table 10. LED Driver (NLED)1 Parameter2 Off-state Output Current (VOUT = VDD) On-state Output Voltage (IOUT = 10 mA) Turn-on Time
3
Symbol IOFF VON tON tOFF
Min -- 0 -- --
Max 10 1.0 10 10
Unit A V s s
Turn-off Time3
1. NLED is an open collector output, so multiple NLED outputs may be used to drive a common LED. 2. Unless otherwise specified, all logic voltages are referenced to DGND. 3. This parameter is not tested in production. It is guaranteed by design and device characterization.
Lucent Technologies Inc.
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L8567 SLIC for People's Republic of China Applications
Data Sheet August 1999
200 TIP RING SWITCH CLOSES < 12 ms 8 F TIP 10 k RING
Electrical Characteristics (continued)
Ring Trip Requirements
s
Ringing signal: -- Voltage, minimum 35 Vrms, maximum 100 Vrms. -- Frequency, 17 Hz to 28 Hz. -- Crest factor, 1.4 to 2. Ringing trip: -- 100 ms (typical), 250 ms (VBAT = -33 V, loop length = 530 ). Pretrip: -- The circuits in Figure 4 will not cause ringing trip.
s
2 F TIP
100 RING
5-5841 (F)
s
Figure 4. Ring Trip Circuits
Table 11. Timing Requirements (DI, EN, DO, and RD), CCLK = 2.048 MHz Symbol tR, tF CIN tPD01 tPDR tSDC tHED tWEN Parameter1 Input Rise and Fall Time EN (10% to 90%)2 Maximum Input Capacitance2 Propagation Delay EN to DO2 Propagation Delay EN to RD Outputs2 Minimum Setup Time from DI to EN2 Minimum Hold Time from EN to DI2 Minimum Pulse Width of EN2 Min 0 -- 0 0 488 488 1465 Max 75 5 977 10 -- -- -- Unit ns pF ns s ns ns s
1. Unless otherwise specified, all times are measured from the 50% point of logic transitions. 2. This parameter is not tested in production. It is guaranteed by design and device characterization.
tWEN
CSEL
CCLK
EN
tSDC RD1, RD2, RD3 B0/B1
tPD01
tHED
NSTAT/NTSD
5-5808a
Figure 5. Timing Requirements 16 Lucent Technologies Inc.
Data Sheet August 1999
L8567 SLIC for People's Republic of China Applications
Test Configurations
VBAT1
0.1 F
VCC
0.1 F
VBAT2
0.1 F TIP 68 RLOOP
VBAT1 PWR VBAT2 PT
BGND
VCC
AGND RD1I RD2I RD3I RD1O RD2O
L8567 SLIC
RING 68 PR
RD3O VTX XMT 51.1 k RCVN 27.4 k 11 k RCVP RCV
DCOUT 63.4 k IPROG B1 B0 EN NSTAT NTSD RTSP RTSN 7.87 k TG VTX CF2 0.1 F CF1 0.1 F
12-2578.e (F)
Figure 6. Basic Test Circuit
Lucent Technologies Inc.
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L8567 SLIC for People's Republic of China Applications
Data Sheet August 1999
Test Configurations (continued)
VBAT OR VCC 100 VS 4.7 F DISCONNECT BYPASS CAPACITOR
100 F PT VS 365 365
+
VM BASIC TEST CIRCUIT PR
-
100 F
VBAT OR VCC PT
VS -----LONGITUDINAL BALANCE = 20 log VM
12-2584 (F)
+
900 VT/R BASIC TEST CIRCUIT PR
Figure 9. Longitudinal Balance
-
ILONG
VS PSRR = 20 log --------VT/R
12-2582 (F)
PT
+
VPT
-
Figure 7. Metallic PSRR
ILONG
-
VPR
BASIC TEST CIRCUIT
+
PR VBAT OR VCC 100 VS 4.7 F ZLONG = VPT VPR OR ILONG ILONG
12-2585 (F)
DISCONNECT BYPASS CAPACITOR
Figure 10. Longitudinal Impedance
VBAT OR VCC 67.5 PT 10 F BASIC TEST CIRCUIT
TG PT 200 680 RG = 7.87 k XMT
VTX
+
0.1 F VT/R BASIC TEST CIRCUIT PR RCV RCV VS
+
VM
67.5 PR 56.3 10 F
-
-
VS PSRR = 20 log -----VM
12-2583 (F)
GXMT =
Figure 8. Longitudinal PSRR
GRCV =
VXMT VT/R VT/R VRCV
12-2587.h (F)
Figure 11. ac Gains 18 Lucent Technologies Inc.
Data Sheet August 1999
L8567 SLIC for People's Republic of China Applications
Test Configurations (continued)
RFI Rejection
Figures 12--14 show the typical RFI rejection performance of the L8567 under the various conditions listed within each figure title. The test circuit is shown below. The input signal is 100 kHz to 100 MHz, 1 Vrms and 2 Vrms, 80% AM, with 1 kHz side tone applied using an R&S T network (CDN). This test is performed to the IEC 801-6 (1994) specification. Note that all power supplies (VCC, VDD, VBAT) are bypassed to ground, as close as possible to the IC, with 1 nF capacitors, and all grounds are shorted on the bottom of the board as close as possible to the IC. Note that no RFI LP filter is used at tip and ring.
1 k VTX TIP
HP* TIMS 4935A
600
R&ST NETWORK
L8567
HP 3580A SPECTRUM ANALYZER
RING
HP 8648C SIGNAL GENERATOR
12-3456 (F)
* HP is a registered trademark of Hewlett-Packard Company.
Figure 12. RFI Rejection Test Circuit
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L8567 SLIC for People's Republic of China Applications
Data Sheet August 1999
Test Configurations (continued)
RFI Rejection (continued)
-50
-60 600 TERMINATION (dBm)
-70
-80
-90
-100
-110 0
10
20
30
40
50
60
70
80
90
100
FREQUENCY IN MHz
12-3471a (F)
Figure 13. RFI Testing, Forward Battery, 600 Loop, No Capacitor, 1 Vrms
-50
-60 600 TERMINATION (dBm)
-70
-80
-90
-100
-110 0 10 20 30 40 50 60 70 80 90 100
FREQUENCY IN MHz
12-3472a (F)
Figure 14. RFI Testing, Forward Battery, 600 Loop, No Capacitor, 2 Vrms
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Lucent Technologies Inc.
Data Sheet August 1999
L8567 SLIC for People's Republic of China Applications
Note also that the T7507 codec will digitally synthesize a termination impedance of 200 + 680 || 100 nF. In order to do this, the codec will assume use of 50 series protection resistors, plus the resistance of the L758X Lucent solid-state switch on both tip and ring. If the L758X switch is not used, the return loss performance will degrade slightly; however, it will still meet MPT standards. Gain flatness will not be affected; however, gain levels will shift less than 0.2 dB. To compensate (if desired), the resistance of the series protection resistor should be increased approximately 20 , to account for the resistance of the switch. Hybrid cancellation is also done digitally by the T7507 codec, assuming a complex hybrid balance network of 200 + 680 || 100 nF. The T7507 codec operates off of a single 5 V power supply. Thus, a line card using the L8567 SLIC and T7507 codec does not require a -5 V supply. Since the T7507 is a 5 V only device, the analog input and output of the T7507 is referenced to 2.5 V. However, the dynamic input range of the L8567 SLIC is high enough to accommodate ac signals referenced to 2.5 V, thus eliminating the need for an external dc blocking capacitor in the receive direction. The basic loop start schematic, using an L8567 SLIC, T7507 codec, and L7583 switch, for PRC termination, is shown in Figure 20. The control logic interface of the L8567 SLIC is matched to the control logic of the T7507. The latched control inputs of the L8567 are designed to be driven by the T7507 control data outputs. The gated supervision outputs of the L8567 SLIC are designed to feed data inputs to the T7507 codec. The T7507 codec supplies the required EN pulses to the L8567 SLIC. Control data to the L8567 and supervision from the L8567 is received from, and passed to, the microcontroller at the serial data interface in the T7507 codec. See the T7507 data sheet for additional details.
Functional Description
General
The L8567 is a full-feature subscriber loop interface circuit (SLIC) designed to provide the battery feed and supervision functions to the tip/ring pair. The device uses a current sense/voltage feed architecture. That is, the device senses tip/ring current and supplies a precise voltage that is proportional to the tip/ring current at the VTX output. The overall transconductance (tip/ring current to VTX voltage gain) is set by a single external resistor, RTG. The voltage at VTX is fed to the codec. The device feeds a precise differential voltage to tip and ring as a function of the signal voltages at the RCVN and RCVP inputs. The codec output is connected to the RCVN/RCVP SLIC inputs.
Use with T7507 Codec for Use in People's Republic of China
The L8567 SLIC and Lucent T7507 codec together form a matched device set designed to meet the specific MPT (Ministry of Post and Telecom) requirements for telephony in the People's Republic of China. The ac interface between the L8567 and the T7507 codec is extremely simple, requiring only a single dc blocking capacitor in the transmit direction, and a short-circuit connection between the codec and SLIC inputs RCVN and RCVP . The T7507 codec has a fixed digital transmit gain stage and two digital gain stages in the receive direction. The choice of gain in the receive direction is user-selectable via a bit in the serial logic input bit stream. The transmit gain of the T7507 codec is such that when the tip/ring to VTX transconductance of the L8567 SLIC is set to 39.75 V/A (RTG = 7.87 k), the overall tip/ring to PCM transmit gain is 0 dB into 813 . (Note that 813 is the equivalent resistance of the PRC complex impedance network of 200 + 680 || 100 nF at 1000 Hz.) The receive gains of the T7507 codec are such that the overall PCM to tip/ring receive gain is user-selectable to either -3.5 dB or -7.0 dB into 813 .
Lucent Technologies Inc.
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L8567 SLIC for People's Republic of China Applications
Data Sheet August 1999 Gain Flatness--Out of Band--High Frequencies
The transmit and receive directions' frequency-dependent loss relative to gain at 3400 Hz is shown below. This specification is met by using the T7507 codec, L8567 SLIC, L7583 solid-state switch, and 50 protection resistors (200 + 680 || 0.1 F termination).
30 25 ACCEPTABLE REGION
Chip Set Performance Specifications
When using the T7507 codec, L8567 SLIC, L7583 solid-state switch, and 50 protection resistors, the following line card requirements are achieved; specified termination impedance is shown in Figure 15.
680 200
0.1 F
5-5324.a
20 LOSS (dB)
Figure 15. Termination Impedance
12.5 10
Gain
Table 12. Gain
0
Gain @ 1020 Hz Transmit Receive* Receive*
Min -0.7 -4.2 -7.7
Typ 0 -3.5 -7.0
Max +0.3 -3.2 -6.7
Unit
-5
dB dB dB
3400
4000 FREQUENCY (Hz)
4600
5000
5-5340
* -3.5 or -7.0 gain mode programmable via the T7507 serial data interface.
Figure 16. Transmit and Receive Direction Frequency-Dependent Loss Relative to Gain at 3400 Hz The loss for frequencies 3400 Hz < f < 4600 Hz is given by: ( 4000 - f ) b = 12.5 1 - sin ---------------------------- dB 1200
Gain Flatness--In Band
Table 13. Gain Flatness--In Band The in-band frequency-dependent loss relative to gain at frequency = 1020 Hz, for the transmit and receive directions. This specification is met by using the T7507 codec, L8567 SLIC, L7583 solid-state switch, and 50 protection resistors (200 + 6800 || 0.1 F termination). Frequency (Hz) 300--400 400--600 600--2400 2400--3000 3000--3400 Min -0.3 -0.3 -0.3 -0.3 -0.3 Max 1.00 0.75 0.35 0.55 1.50 Unit dB dB dB dB dB
Gain Flatness--Out of Band--Low Frequencies
Table 14. Gain Flatness--Out of Band--Low Frequencies Transmit direction only, loss relative to 1020 Hz. This specification is met by using the T7507 codec, L8567 SLIC, L7583 solid-state switch, and 50 protection resistors (200 + 680 || 0.1 F termination).
Frequency (Hz) 16.67 40 50 60 Min Loss (dB) 30 26 30 30
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Lucent Technologies Inc.
Data Sheet August 1999
L8567 SLIC for People's Republic of China Applications Return Loss
The following template is achieved.
Chip Set Performance Specifications
(continued)
Loss vs. Level Relative to Loss at -10 dBm Input at 1020 Hz
18
This specification is met by using the T7507 codec, L8567 SLIC, L7583 solid-state switch, and 50 protection resistors (200 + 680 || 0.1 F termination).
RL (dB)
14
300 500 1.6
2000
3400
FREQUENCY (Hz)
5-5325
Figure 18. Return Loss
0.6 LOSS (dB) 0.3 0 -0.3 -0.6 20 TBRL (dB) -1.6 16 -55 -50 -40 -10 +3 dBm0
Hybrid Balance
The following template is achieved.
300 500
5-5341
2500
3400
FREQUENCY (Hz)
5-5326
Figure 17. Loss vs. Level Figure 19. Hybrid Balance
Lucent Technologies Inc.
23
VBAT1
VDD VCC
BGND
DGND
AGND AGND
CF1
0.1 F VBAT CBAT1 CDD CCC
0.1 F
0.1 F
CF1 0.1 F 0.47 F CF2
CF2
24
RPROG 63.4 k IPROG DCOUT TG RTG 7.87 k CB2 DX VFXIN DR VTX 0.1 F PCM HIGHWAY VBAT2 PWR VBAT2 CBAT2 0.1 F TO TEST BUS RD1I RD2I RD3I TRING RCVN TBAT PT RCVP VFROP FSEP IFS 1/4 T7507 CODEC PR L8567 SLIC EN1 EN2 TSD INTESTin INTESTout B0 RTSP 2.0 M RTSP NSTAT NTSD RD1C RD2C RD3C RTSN RTS2 274 k VRING RTSN 2.0 M NTSD0 AGND NTSD1--3 RTS1 402 CRTS2 0.27 F CRTS1 0.022 F B1 EN3 B0C B1C NSTATC NTSDC EN EN0 SYNC L7583 SWITCH RBAT FGND VFRON TLINE DXEN MCLK CSEL CCLK DI DO TIMING AND CONTROL INRING LATCH RRING VDD 0.1 F CDD TO L8567 TO SLIC AND L8567 L7583 SLIC SWITCH 1, 2, 1, 2, OR 3 AND 3 FROM L8567 SLIC 1, 2, AND 3 FROM L7583B 1, 2, AND 3 TO L7583B 1, 2, AND 3
Applications
CROWBAR PROTECTOR
RPT
TIP
50
RPR
RING
50
L8567 SLIC for People's Republic of China Applications
Figure 20. Basic Loop Start Application Using T7507 Codec and L7583 Switch for 200 + (680 Complex Termination and Hybrid Balance
CROWBAR PROTECTOR
|| 100 nF)
12-3366a (F)
Lucent Technologies Inc.
Data Sheet August 1999
Data Sheet August 1999
L8567 SLIC for People's Republic of China Applications
Applications (continued)
Table 15. Parts List for Loop Start Application Name Integrated Circuits SLIC Protector Ringing and Test Access Codec Overvoltage Protection RPT RPR Power Supply CBAT1/CBAT2 CCC CDD CF1 CF2 dc Profile RPROG RPWR (with single battery supply) ac Characteristics CB2 RTG Supervision RTS1 RTS2 CRTS1 CRTS2 RTSN RTSP Value L8567 Crowbar L7583B T7507 Protector1 Function Subscriber loop interface circuit (SLIC). Secondary protection. Switches ringing signals and test buses. Transmit/receive gains, termination impedance, hybrid balance, D/A, A/D, and filtering. Protection resistor. PTC or fusible. Protection resistor. PTC or fusible. VBAT filter capacitors. VCC filter. VDD filter. With CF2, improves idle-channel noise. With CF1, improves idle-channel noise. Sets dc loop current limit. Limits power dissipated on the SLIC, provides dc power to the loop. ac/dc separation capacitor. Sets SLIC transconductance. Ringing source series resistor. With CRTS2, forms first pole of a double pole, 2 Hz ring trip sense filter. With RTSN, RTSP forms second 2 Hz filter pole. , With RTS2, forms first 2 Hz filter pole. With CRTS1, RTSP forms second 2 Hz filter pole. , With CRTS1, RTSN, forms second 2 Hz filter pole.
50 50 0.1 F, 20%, 100 V 0.1 F, 20%, 10 V 0.1 F, 20%, 10 V 0.47 F, 20%, 100 V 0.1 F, 20%, 100 V 63.4 k, 1%, 1/16 W 2.2 k, 5%, 2 W
0.1 F, 20%, 100 V 7.87 k, 1%, 1/16 W 402 , 5%, 2 W 274 k, 1%, 1/16 W 0.022 F, 20%, 5 V 0.27 F, 20%, 100 V 2 M, 1%, 1/16 W 2 M, 1%, 1/16 W
1. Contact your Lucent Technologies account representative for protector recommendations. Choice of this (and all) component(s) should be evaluated and confirmed by the customer prior to use in any field or laboratory system. Lucent does not recommend use of this part in the field without performance verification by the customer. This device is suggested by Lucent for customer evaluation. The decision to use a component should be based solely on customer evaluation.
Lucent Technologies Inc.
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L8567 SLIC for People's Republic of China Applications
Data Sheet August 1999
Applications (continued)
Design Considerations
Table 16 shows the design parameters of the application circuit shown in Figure 20. Components that are adjusted to program these values are also shown. Table 16. 200 + 680
|| 0.1 F Design Parameters
Parameter Value 11 mA 40 mA 246 3.17 dBm 200 + 680 0 dB -3.5 dB/-7.0 dB Components Adjusted -- RPROG RPT, RPR, L7583 -- Set via T7507 Set via T7507 Set via T7507 Set via T7507
Design Parameter Loop Closure Threshold dc Loop Current Limit dc Feed Resistance 2-wire Signal Overload Level ac Termination Impedance Hybrid Balance Line Impedance Transmit Gain Receive Gain
|| 0.1 F 200 + 680 || 0.1 F
26
Lucent Technologies Inc.
Data Sheet August 1999
L8567 SLIC for People's Republic of China Applications
Applications (continued)
50
Characteristic Curves
LOOP CURRENT (mA) 40
1 10 k
0 -10 -20 PSRR (dB) -30 -40 -50 -60 -70 -80 10 104 105 106
BELOW CURRENT LIMIT CURRENT LIMIT
30 1 RDC 20
10
0 0 5 10 15 20 25 30 35 40 45
LOOP VOLTAGE (V)
12-3050.g (F)
VBAT1 = VBAT2 = -48 V. ILIM = 40 mA (RPROG = 66.5 k). 100 1000
FREQUENCY (Hz)
12-2830 (F)
Figure 23. L8567 Loop Current vs. Loop Voltage
Figure 21. L8567 Typical VCC Power Supply Rejection
0.030 ILOOPdc 0.028 0.026 IBAT1
0 -10 -20 PSRR (dB) -30 -40 -50 -60 -70 -80 10 100 1000 104 105 106 FREQUENCY (Hz)
12-2871 (F)
0.024 0.022 BATTERY/LOOP OUTPUT (mA)
CURRENT LIMIT
IBAT2
0.020 0.018 0.016 0.014 0.012 0.010 0.008 0.006 0.004 0.002 0.000 0 200 400 600 800 1000 RLOOP ()
12-3470 (F)
BELOW CURRENT LIMIT
Figure 22. L8567 Typical VBAT Power Supply Rejection
Figure 24. L8567 Loop/Battery Current (with Battery Switch) vs. Loop Resistance Lucent Technologies Inc. 27
L8567 SLIC for People's Republic of China Applications
Data Sheet August 1999
If the active power dissipated in the SLIC is too high, the SLIC temperature will rise above the thermal shutdown threshold and the SLIC will be driven into a thermal shutdown state. The worst case is under short dc loops at elevated ambient temperatures. The power dissipated on the SLIC must be controlled to avoid forcing the SLIC into thermal shutdown during an active phone conversation. With the L8567 SLIC, short-loop power dissipation may be controlled using several user-selectable techniques. The first involves use of a lower-voltage auxiliary battery. This will reduce the total short-loop off-hook power. This has the advantage of not only controlling the SLIC temperature rise, but also minimizing total power drawn from the talk battery. If the user chooses not to provide an auxiliary battery, the power dissipated by the SLIC must be controlled in some other manner. With the L8567 SLIC, this may be done in two ways. One technique involves the use of a single external power control resistor. This technique does not minimize total power dissipation; rather it controls the power that it is dissipating through the SLIC package by removing some power from the SLIC through the resistor, thus avoiding excess temperature rise. Because of the higher thermal impedance associated with the 32-pin PLCC, this technique may be necessary with the 32-pin PLCC package option. The other technique is simply to choose the 44-pin PLCC package option. The thermal resistance of the 44-pin PLCC is low enough to ensure, under most conditions, that the thermal shutdown temperature of the SLIC is not exceeded. Power dissipation calculations should be made to assess design margin. For the three configurations discussed above, connections to the VBAT1, VBAT2, and PWR nodes are outlined in the table below. Table 17. Power Connections Option 32 PLCC with auxiliary battery 32 PLCC with highvoltage battery and power resistor Connections to Power Mode VBAT2 PWR VBAT1 VBAT2 VBAT2 VBAT1 VBAT1 VBAT1 VBAT1 through power control resistor VBAT1
Applications (continued)
Characteristic Curves (continued)
2000 STILL AIR 47 C/W 44 PLCC 1500 POWER (mW)
1000 32 PLCC 500
0 20
40
60
80
100
120
140
160 180
AMBIENT TEMPERATURE, TA (C)
12-2825.b (F)
Note: Curve is relevant only to portion of total power dissipation that is actually dissipated on the SLIC.
Figure 25. Power Derating
Power Control
The total power drawn from the talk battery during an off-hook state is the product of the battery voltage times the total dc loop current, plus the SLIC quiescent power dissipation. Note that during the on-hook state, the power is simply the SLIC quiescent power. PTOTAL(off-hook) = VBAT * ILOOP + PSLIC(quiescent) A portion of the total power is dissipated in the subscriber loop, and a portion of the total power is dissipated in the SLIC itself. The loop power is used to drive the handset and is given by: PLOOP = I2LOOP * RLOOP ILOOP is the dc loop current. In the short dc loops, the dc loop current will be limited by the SLIC. In the case of the L8567 SLIC, the dc loop current is determined by external resistor RPROG. RLOOP is the sum of the actual loop resistance (wire resistance and dc handset resistance) plus any protection or other series resistance. The active or off-hook power dissipated in the SLIC is simply the difference of the total power drawn from the talk battery, less the loop power, less the SLIC quiescent or on-hook power. PSLIC(active) = PTOTAL - PLOOP - PSLIC(on-hook) 28
44 PLCC with highvoltage battery
VBAT1
VBAT1
Lucent Technologies Inc.
Data Sheet August 1999
L8567 SLIC for People's Republic of China Applications Power Control--32-Pin PLCC with Power Control Resistor
This section is applicable if the user chooses to use a single high-voltage battery with an external power control resistor. The power resistor is used in conjunction with the 32-pin PLCC package. Resistor RPWR is connected from pin PWR to the battery supply. This resistor limits the power that is dissipated on the SLIC. dc loop current is shared between the SLIC and RPWR, thus controlling the actual power that is dissipated on the SLIC. The value and power rating of RPWR is determined by the thermal capabilities of the L8567's 32-pin PLCC package. The value and power rating of RPWR is calculated as shown below. The relationship for the power dissipated in the SLIC is given by: PSLIC = PTOTAL + PQ - PPROT - PPWR - PLOOP Where: PSLIC = the power dissipated in the SLIC. PTOTAL = the total off-hook power dissipation. PQ = the SLIC quiescent or on-hook power dissipation. PPROT = the power dissipated in the protection resistors (and L758X switch). PPWR = the power dissipated in RPWR. PLOOP = the power dissipated in the subscriber loop. The relationships for the individual power dissipation components are: PTOTAL = ILOOP * |VBAT| (2) (1)
Applications (continued)
Power Control--Auxiliary Battery
With the auxiliary battery technique under long loops, the entire L8567 draws power from the higher-voltage battery. As the loop length decreases and the loop current increases or limits, the final output drive stage of the L8567 SLIC will draw power from the lowervoltage auxiliary battery. Thus, for a given loop, with a given loop current requirement, the minimum battery voltage is used by the L8567 SLIC, which minimizes the total power consumed. During on-hook or opencircuit conditions, the high battery is seen at tip and ring. All circuits on the L8567, other than the final output drive stage, are powered by the higher-voltage battery regardless of dc loop length. Thus, SLIC quiescent power will be determined solely by the high-voltage battery and will not be reduced under short dc loops. Tip/ring voltage varies as a function of loop length, decreasing with decreasing loop length. The battery transition will occur when the tip/ring voltage is less than VBAT2 by a diode drop and a VCE(SAT), or about 1 V. Thus, the transition point from VBAT1 to VBAT2 may be controlled by the choice of VBAT2. The relationship is given below: VBAT2 = TOH + RDC(TIP) * ILOOP + 2 * RPROT * ILOOP + RLOOP * ILIM + RDC(RING) * ILIM + (VDIODE + VCE(SAT)) where: VBAT2 = magnitude of auxiliary battery. TOH = overhead voltage tip to ground, typically 2.5 V. RDC(TIP) = dc feed resistance on tip, typically 55 . ILOOP = loop current. VBAT2 will switch under short-loop conditions where it is likely that the SLIC will be current limiting; thus, ILOOP = ILIM. RPROT = series protection resistance plus L758X resistance, nominal 68 . RLOOP = loop resistance for transition from VBAT1 to VBAT2. ILIM = SLIC current limit set per resistor RLIM. RDC(RING) = dc feed resistance on ring, typically 55 . (VDIODE + VCE(SAT)) = internal voltage drop associated with battery switch circuit, typically 1 V. Thus, the equation may be rewritten: VBAT2 = 2.5 V + 55 ILIM + 132 ILIM + RLOOP ILIM + 55 ILIM + 1V VBAT2 - 3.5 RLOOP = -------------------------------- - 242 ILIM Thus, for example, for a nominal loop transition at 700 , with a 25 mA current limit, VBAT2 should be nominal 27 V. Lucent Technologies Inc.
PQ is the active state open loop power dissipation of the L8567 SLIC and is specified in Table 4 on page 12. PPROT = (ILOOP)2 * 2RP ( VBAT - VROH - VLOOP ) PPWR = ------------------------------------------------------------------------( RPWR ) PLOOP = VLOOP * ILOOP Where: ILOOP is the maximum dc loop current which is the dc loop current limit that is set by resistor RPROG. RP is the value of the protection resistor plus the resistance of the L758X switch. |VBAT| is the magnitude of the maximum battery voltage. VROH is the overhead voltage associated with the ring lead. VLOOP is the ring/tip loop voltage. This voltage is a function of the dc loop length or resistance. It will decrease with decreasing loop resistance. RPWR is the resistance of the external resistor RPWR. 29
2
(3) (4) (5)
L8567 SLIC for People's Republic of China Applications
Data Sheet August 1999 Power Considerations
RPWR Design Example: Assume ILOOP = 45 mA. This assumes that a 40 mA current limit is programmed by resistor RPROG set at 63.4 k, plus a worst-case 15% tolerance that is specified in Table 5. |VBAT| = 56 V. 2RP = 136 . This assumes use of 50 PTC in both the tip and ring lead associated with the L7583 ON resistance. VROH = 4 V (typical). PQ = 165 mW as nominally specified in Table 4. TTSD = 165 C per Table 4. TA = 85 C. JA = 60 C/W per Table 4. VLOOP is varied from the open-circuit voltage of approximately 50 V to the voltage at a 100 loop length, approximately 5 V. First, using equations 6 and 7, calculate the maximum allowed power dissipation in the SLIC.
TTSD - TA = TRISE
Applications (continued)
Power Control--32-Pin PLCC with Power Control Resistor (continued)
The maximum power that may be dissipated in the SLIC, PSLIC(MAX) is given by
TTSD - TA = TRISE
(6) (7)
TRISE PSLIC ( MAX ) = --------------JA Where:
TTSD is the thermal protection shutdown temperature and is specified in Table 4. TA is the maximum ambient operating temperature. TRISE is the maximum allowed SLIC temperature rise to avoid driving the SLIC into thermal shutdown. PSLIC(MAX) is the maximum allowed power that is dissipated on the SLIC to avoid driving the SLIC into thermal shutdown. JA is the thermal resistance, junction to ambient of the 32-pin PLCC package; it is specified in Table 4 on page 12. The approach to choosing the value and rating of RPWR follows. First use equations 6 and 7 to determine the maximum allowed power that may be dissipated on the SLIC without driving the SLIC into thermal shutdown. Next consider equations 1 and 4. In both equation 1 and 4, pick a value of RPWR and for this value, or RPWR, vary VLOOP from the open-circuit (on-hook) state voltage to the voltage seen at the minimum expected dc loop length (100 ). The idea is to use the SLIC power dissipation value from equation 1, PSLIC, to ensure that the maximum SLIC power dissipation value from equation 7, PSLIC(MAX), is not exceeded for any value of loop length. At the same time, using equation 4, try to minimize the power dissipated in RPWR so as to choose the minimum power rating of the resistor to minimize cost associated with this resistor. This technique is illustrated in the following design example.
(6)
165 C - 85 C = 80 C TRISE PSLIC ( MAX ) = --------------JA 80 C PSLIC(MAX) = ---------------- = 1.33 W 60 C Given the choice of RPWR chosen, the value of PSLIC in equation 8 must be less than 1.33 W for all loop lengths (all values of VLOOP in equation 1). At the same time, RPWR should be chosen to minimize PPRW from equation 4. Inserting values into equation 1: PSLIC PTOTAL + PQ - PPROT - PPWR - PLOOP From equation 2, 3, 4, 5 PSLIC ILOOP * |VBAT| + PQ - (ILOOP)2 * ( VBAT - VROH - VLOOP ) 2RP - ------------------------------------------------------------------------- - VLOOP * ILOOP RPWR Inserting values: 1.33 W < (0.045)(56) + 0.165 W - [(0.045) 2 * ( 56 - 4 - VLOOP ) 2(50 + 18)] - ------------------------------------------------------ - RPWR (VLOOP)(0.045 mA) (9) Lucent Technologies Inc.
2 2
(7)
(8)
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Data Sheet August 1999
L8567 SLIC for People's Republic of China Applications
SLIC power will exceed 1.33 W; thus, 4400 is not appropriate. This result suggests that the minimum power rating of RPWR under the assumed conditions is 1 W. Table 22 and Table 23 show results for 2200 with a +5% and -5% variation, respectively. These tables suggest that a 5% tolerance is adequate for RPWR. (10) Table 18. RPWR = 2600 PSLIC (W) 1.334985 1.281138 1.208062 1.115754 1.004215 0.873446 0.723446 0.554215 0.365754 0.158062 VLOOP (V) 5 10 15 20 25 30 35 40 45 50 RPWR () 2600 2600 2600 2600 2600 2600 2600 2600 2600 2600 PPWR (W) 0.849615 0.678462 0.526538 0.393846 0.280385 0.186154 0.111154 0.055385 0.018846 0.001538
Applications (continued)
Power Considerations (continued)
Inserting values into equation 4: ( VBAT - VROH - VLOOP ) PPWR = ------------------------------------------------------------------------RPWR ( 56 - 4 - VLOOP ) PPWR = -----------------------------------------------------RPWR
2 2
At this point, the idea is to choose a value of RPWR, and vary VLOOP from the on-hook value of approximately 50 V to the very short loop (~100 ) value of 5 V in both equations 9 and 10. For the choice of RPWR, the relationship in equation 9 must be met to ensure that sufficient power is dissipated in RPWR to ensure that L8567 SLIC is not driven into thermal shutdown. At the same time, for the choice of RPWR, equation 10 will tell what the power rating of RPWR needs to be. Obviously, it is desirable to minimize PPRW in equation 10 to minimize the cost associated with component RPWR. An easy way to vary VLOOP for various values of RPWR is to use a computer-based spreadsheet program. Table 18 shows a spreadsheet for the choice of RPWR = 2600 . As shown, for this choice of resistor under short loop conditions, the power dissipated in the SLIC exceeds 1.33 W; thus, the SLIC may be driven into thermal shutdown. Therefore, 2600 is not an appropriate choice of RPWR. In Table 19, RPWR was reduced to 2200 . As shown in this spreadsheet, under no loop conditions does the SLIC power dissipation exceed 1.33 W. Thus, in terms of SLIC power dissipation, 2200 is an appropriate choice. Looking at the power dissipated in resistor RPWR, the maximum power dissipation is 0.96 W, which says a rating of 2 W (with margin) is appropriate for 2200 . In Table 20, RPWR was further reduced to 1800 . Again, with this choice, the SLIC power does not exceed 1.33 W, so in terms of SLIC power dissipation, 1800 is also an appropriate choice. However, with 1800 , the power dissipated in RPWR under short loop conditions exceeds 1 W, which suggests that for 1800 , the power rating of RPWR should be greater than 2 W. Thus, while 1800 ensures the SLIC will not be driven into thermal shutdown, because of the higher power rating required compared to 2200 , 2200 is a better choice. In Table 21, RPWR was increased to 4400 . This is the minimum value to get the power rating of RPWR to a 0.5 W resistor. However, with this choice of resistor, the Lucent Technologies Inc.
Table 19. RPWR = 2200 PSLIC (W) 1.180509 1.157782 1.112327 1.044145 0.953236 0.8396 0.703236 0.544145 0.362327 0.157782 VLOOP (V) 5 10 15 20 25 30 35 40 45 50 RPWR () 2200 2200 2200 2200 2200 2200 2200 2200 2200 2200 PPWR (W) 1.004091 0.801818 0.622273 0.465455 0.331364 0.22 0.131364 0.065455 0.022273 0.001818
Table 20. RPWR = 1800 PSLIC (W) 0.957378 0.9796 0.974044 0.940711 0.8796 0.790711 0.674044 0.5296 0.357378 0.157378 VLOOP (V) 5 10 15 20 25 30 35 40 45 50 RPWR () 1800 1800 1800 1800 1800 1800 1800 1800 1800 1800 PPWR (W) 1.227222 0.98 0.760556 0.568889 0.405 0.268889 0.160556 0.08 0.027222 0.002222 31
L8567 SLIC for People's Republic of China Applications
Data Sheet August 1999 Power Control--44-Pin PLCC Package
With the 44-pin PLCC, the thermal impedance of the package is probably enough to ensure the SLIC thermal shutdown temperature is not exceeded. Power calculations, as illustrated below, should be made to ensure design margin. The still-air thermal resistance of the 44-pin PLCC is 47 C/W; however, this number implies zero airflow as if the L8567 were totally enclosed in a box. A more realistic number would be 43 C/W. This is an experimental number that represents a thermal impedance with no forced airflow (i.e., from a muffin fan), but from the natural airflow as seen in a typical switch cabinet. The SLIC will enter the thermal shutdown state at typically 165 C. The thermal shutdown design should ensure that the SLIC temperature does not reach 165 C under normal operating conditions. Assume a maximum ambient operating temperature of 85 C, a maximum current limit of 45 mA, and a maximum battery of -52 V. Further, assume a (worst case) minimum dc loop of 100 and that 100 protection resistors are used at both tip and ring. 1. TTSD - TA(max) = allowed thermal rise. 165 C - 85 C = 80 C 2. Allowed thermal rise = package thermal impedance * SLIC power dissipation. 80 C = 43 C/W * SLIC power dissipation SLIC power dissipation (PD) = 1.9 W Thus, if the total power dissipated in the SLIC is less than 1.9 W, it will not enter the thermal shutdown state. Total SLIC power is calculated as: Total PD = Maximum battery * Maximum current limit + SLIC quiescent power. For the L8567, SLIC quiescent power (PQ) is approximated at 0.167 W. Thus, Total PD = (-52 V * 45 mA) + 0.167 W Total PD = 2.34 W + 0.167 W Total PD = 2.507 W The power dissipated in the SLIC is the total power dissipation less the power that is dissipated in the loop. SLIC PD = Total power - Loop power Loop power = (ILIM)2 * (RdcLOOP min + 2RP) Loop power = (45 mA)2 * (100 + 200 ) Loop power = 0.61 W SLIC power = 2.507 W - 0.61 W SLIC power = 1.897 W < 1.9 W Thus, in this example, the thermal design ensures that the SLIC will not enter the thermal shutdown state. Lucent Technologies Inc.
Applications (continued)
Power Considerations (continued)
Table 21. RPWR = 4400 PSLIC (W) 1.682555 1.558691 1.423464 1.276873 1.118918 0.9496 0.768918 0.576873 0.373464 0.158691 VLOOP (V) 5 10 15 20 25 30 35 40 45 50 RPWR () 4400 4400 4400 4400 4400 4400 4400 4400 4400 4400 PPWR (W) 0.502045 0.400909 0.311136 0.232727 0.165682 0.11 0.065682 0.032727 0.011136 0.000909
Table 22. RPWR = 2310 (RPWR = 2200 + 5%) PSLIC (W) 1.228323 1.195964 1.141959 1.06631 0.969016 0.850076 0.709492 0.547262 0.363388 0.157868 VLOOP (V) 5 10 15 20 25 30 35 40 45 50 RPWR () 2310 2310 2310 2310 2310 2310 2310 2310 2310 2310 PPWR (W) 0.956277 0.763636 0.592641 0.44329 0.315584 0.209524 0.125108 0.062338 0.021212 0.001732
Table 23. RPWR = 2090 (RPWR = 2200 - 5%) PSLIC (W) 1.127662 1.115581 1.079576 1.019648 0.935796 0.828021 0.696322 0.5407 0.361155 0.157686 VLOOP (V) 5 10 15 20 25 30 35 40 45 50 RPWR () 2090 2090 2090 2090 2090 2090 2090 2090 2090 2090 PPWR (W) 1.056938 0.844019 0.655024 0.489952 0.348804 0.231579 0.138278 0.0689 0.023445 0.001914
32
Data Sheet August 1999
L8567 SLIC for People's Republic of China Applications
The dc feed characteristic can be described by: IL = VBAT - VOH --------------------------------RL + 2RP + Rdc
dc Characteristics
The L8567 SLIC operates in a dc unbalanced mode. In the forward active state, under open-circuit (on-hook) conditions, the tip to ring voltage will be a nominal 7.1 V less than the battery. This is the overhead voltage. The tip and ring overhead is achieved by biasing ring a nominal 4.6 V above battery and by biasing tip a nominal 2.5 V below ground. During off-hook conditions, some dc resistance will be applied to the subscriber loop as a function of the physical loop length, protection, and telephone handset. As the dc resistance decreases from infinity (on-hook) to some finite value (off-hook), the tip to ring voltage will decrease as shown below.
RL + 2RP + Rdc Where: IL = dc loop current. VT/R = dc loop voltage. |VBAT| = battery voltage magnitude. VOH = overhead voltage. This is the difference between the battery voltage and the open loop tip/ring voltage. RL = loop resistance, not including protection resistors. RP = protection resistor value. Rdc = SLIC internal dc feed resistance. The design begins by drawing the desired dc template.
VT/R =
( VBAT - VOH ) x RL -------------------------------------------
VTIP TO GND ON HOOK (1/2)Rdc
Refer to Figures 23, 24, and 26. Starting from the on-hook condition and going through to a short circuit, the curve passes through two regions: Region 1; On-hook and low loop currents: The slope corresponds to the dc resistance of the SLIC, Rdc1 (plus any series resistance). The open-circuit voltage is the battery voltage less the overhead voltage of the device, VOH (7.0 V typical). Region 2; Current limit: The dc current is limited to a value determined by external resistor RPROG. This region of the dc template has a high resistance (10 k). Calculate the external resistor as follows: RPROG (k) = 1.59 ILIM (mA) Notice that the I/V curve is uninterrupted when the power is shifted from the high-voltage battery to the low-voltage battery (if auxiliary battery option is used), if the transition occurs in the current-limit region of operation. This is shown in Figure 24.
BEGIN CURRENT LIMITING (1/2)Rdc + RLIM (1/2)Rdc
VBAT
DECREASING LOOP LENGTH
12-3431 (F)
Figure 26. Tip/Ring Voltage Decrease As illustrated above, as loop length decreases, the tip to ground voltage will decrease with a slope corresponding to one-half the internal dc feed resistance of the SLIC. (The L8567 dc feed resistance is a nominal 110 .) The ring to ground voltage will also decrease with a slope corresponding to one-half the internal dc feed resistance of the SLIC, until the SLIC reaches the current-limit region of operation. At that point, the slope of the ring to ground voltage will increase to the sum of one-half the internal dc feed resistance of the SLIC plus approximately 10 k, which is the slope of the I/V characteristic in the current-limit region.
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L8567 SLIC for People's Republic of China Applications
Data Sheet August 1999
dc Characteristics (continued)
Loop Range
The following equation is used to determine the dc loop range. VBAT - VOH RL = -------------------------------- - 2RP - Rdc IL Where: RL = dc loop range. |VBAT| = magnitude of battery voltage. VOH = SLIC overhead voltage. IL = dc loop current. RP = series protection resistor and resistance of L758X solid-state switch (if used). Rdc = SLIC dc feed resistance. Example 1, Standard Loop: Calculate loop range with battery voltage of 48 V, SLIC maximum overhead of 7.8 V, SLIC dc feed resistance of 65 , 18 mA loop current requirement, worst-case resistance of L758X switch of 28 , and 50 protection resistor with worst-case 10% tolerance of 55 . 48 V - 7.8 V RL = ------------------------------------ - ( 2 x ( 55 + 28 ) ) - 130 0.018 A RL = 1937 > 1800 Example 2, Extended Loop: With a -65 V battery voltage, assuming a SLIC nominal overhead of 7.1 V, SLIC dc feed resistance of 110 , 18 mA loop current requirement, worst-case resistance of L758X switch of 28 , and 50 protection resistor with worst-case 10% tolerance of 55 , what is the maximum loop length? 65 V - 7.1 V 2941 = ------------------------------------ - ( 2 x ( 55 + 28 ) ) - 110 0.018 A
dc Applications
On-Hook Transmission
In order to drive an on-hook ac signal, the SLIC must set up the tip and ring voltage to a value less than the battery voltage. The amount that the open loop voltage is decreased relative to the battery is referred to as the overhead voltage. Expressed as an equation, VOH = |VBAT| - (VPT - VPR) Without this buffer voltage, amplifier saturation will occur and the signal will be clipped. The L8567 is automatically set at the factory to allow undistorted on-hook transmission of a 3.17 dBm signal into a 900 ac loop impedance. The drive amplifiers are capable of 4 Vrms minimum (VAMP). So, the maximum signal the device can guarantee is: ZT/R VT/R = 4 V ------------------------- ZT/R + 2RP The peak voltage at output of tip and ring amplifiers is related to the peak signal voltage by:
2RP vT/R 1 + ----------- ZT/R
Vamp =
RP + VT/R - RP [ZT/R] + VAMP -
12-2563 (F)
Figure 27. SLIC 2-Wire Output Stage
34
Lucent Technologies Inc.
Data Sheet August 1999
L8567 SLIC for People's Republic of China Applications Supervision
Both the loop closure and ring trip supervision functions are included on the L8567 SLIC. The outputs of these two supervision functions are internally wiredORed together to form a single output NSTAT. The wired-OR connection of the loop supervision and ring trip detector is also available on pin NLED. This pin has sufficient drive capability to drive an LED. This pin is an open-collector output, so multiple pins can be used to drive a common LED. Also included is a SLIC thermal shutdown indicator, NTSD. Note that the ring trip detector is not active in the lowpower scan state. The ring trip detector must be active prior to applying power ringing to the subscriber loop. Activate the ring trip detector by putting the L8567 SLIC into the powerup mode before applying power ringing to the subscriber loop.
dc Applications (continued)
On-Hook Transmission (continued)
In addition to the required peak signal level, the SLIC needs about 2 V from each power supply to bias the amplifier circuitry. It can be thought of as an internal saturation voltage. Combining the saturation voltage and the peak signal level, the required overhead can be expressed as: VOH 2RP = VSAT + 1 + ----------- vT/R ZT/R
where VSAT is the combined internal saturation voltage between the tip/ring amplifiers and VBAT (4.0 V typical). RP () is the protection resistor value. ZT/R () is the ac loop impedance. Example: Determine the required overhead to transmit on-hook (ILOOP = 0) a 3.17 dBm ac signal into a 900 ac lead. Assume use of 50 protection resistors with a 10% tolerance or 55 and an L7583 solid-state switch. The worst-case resistance of the switch is 28 . Note the minimum overhead voltage of the L8567 is 6.4 V. 2 x [ 55 + 28 ] VON = 4.0 + 1 + --------------------------------- 2 ( Vrms ) - 900
[ Vrms ] - ---------------------- 900 3.17 dBm = 20log -----------------------------3
2
Loop Closure
The on-hook to off-hook loop closure threshold is internally set to a nominal 11 mA at VBAT = -48 V. There is a nominal 2 mA hysteresis. This means that the off-hook to on-hook threshold will be a nominal 2 mA less than the on-hook to off-hook threshold. The loop closure threshold will track with battery voltage, increasing as the battery gets more negative. The loop closure comparator has built-in longitudinal rejection, eliminating the need for an external 50 Hz/60 Hz filter. The loop closure detector is valid during scan, forward, and reverse active states.
10
Vrms = 1.296 V 2 x [ 55 + 28 ] VON = 4.0 + 1 + --------------------------------- 2 ( Vrms ) - 900 Vrms = 1.296 V 2 [ 55 + 28 ] VON = 4.0 + 1 + --------------------------- ( 2 ) ( 1.296 ) - 900 VOH = 6.17 V < 6.4 V Thus, an overhead of 6.17 V is needed for on-hook transmission of a 3.17 dBm signal into a 900 ac load. The L8567 has a minimum overhead of 6.4 V.
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L8567 SLIC for People's Republic of China Applications
Data Sheet August 1999
dc Applications (continued)
Ring Trip Detection
The ring trip circuit is a comparator that has a special input section optimized for this application. The equivalent circuit is shown in Figure 28, along with its use in an application using unbalanced, battery-backed ringing.
PHONE HOOK SWITCH
RLOOP RTSP RC PHONE RTS1 402 RTS2 274 k VRING VBAT
12-3014 (F)
RTSP + IP = IN IN - RTSN 15 k + - 7V NRDET
2 M CRTS2 0.27 F RTSN 2 M CRTS1 0.022 F
Figure 28. Ring Trip Equivalent Circuit and Equivalent Application The comparator input voltage compliance is VCC to VBAT, and the maximum current is 240 A in either direction. Its application is straightforward. A resistance (RTSN + RTS2) in series with the RTSN input establishes a current that is repeated in the RTSP input. A slightly lower resistance (RTSP) is placed in series with the RTSP input. When ringing is being injected, no dc current flows through RTS1, and so the RTSP input is at a lower potential than RTSN. When enough dc loop current flows, the RTSP input voltage increases to trip the comparator. In Figure 28, a low-pass filter with a double pole at 2 Hz was implemented to prevent false ring trip. The following example illustrates how the detection circuit of Figure 28 will trip at 12.5 mA dc loop current using a -48 V battery. -7 V - (-48 V) IN = ------------------------------------2.289 M = 17.9 A The current IN is repeated as IP in the positive comparator input. The voltage at comparator input RTSP is: VRTSP = VBAT + ILOOP(dc) x RTS1 + IP x RTSP Using this equation and the values in the example, the voltage at input RTSP is -12 V during ringing injection (ILOOP(dc) = 0). Input RTSP is, therefore, at a level of 5 V below RTSN. When enough dc loop current flows through RTS1 to raise its dc drop to 5 V, the comparator will trip. In this example, 5V ILOOP ( dc ) = ---------------402 = 12.5 mA 36 Lucent Technologies Inc.
Other Supervision Functions
The L8567 has on-chip thermal shutdown circuitry. If the silicon die temperature exceeds a nominal 165 C temperature, the SLIC will sense this temperature and enter the thermal shutdown mode, regardless of the logic inputs. The thermal shutdown mode is functionally similar to the disconnect state. When the die temperature cools, the SLIC will return to the reshutdown state. A hysteresis is included in the thermal shutdown mechanism. The L8567 also has a logic input pin, NEXTSD, whose status is transferred to the serial output data bus. This pin may be connected to an external monitoring device. An example is the thermal shutdown output pin of the L7583. If the L7583 enters the thermal shutdown mode, this is reflected in the TSD output pin of this device. The L8567 SLIC can accept this status pin and transfer the information on this pin to the serial output data bus.
Data Sheet August 1999
L8567 SLIC for People's Republic of China Applications
L7583 solid-state switch is used instead of EMRs, the logic control outputs from the codec will go directly to the state control inputs of the switch. In this mode of operation, the relay drivers on the L8567 SLIC are not used. If this is the case, tie the logic inputs RD1I, RD2I, and RD3I to ground. This will force the drivers into the not-active state, which is the state with the lowest power consumption. For the SLIC logic inputs, the latch is controlled by input EN. When EN is high, the input data latches are active; that is, data at the B0, B1, RD1I, RD2I, and RD3I inputs are latched. The latched data will control the state of the SLIC and drivers, and the SLIC and drivers will not respond to changes at the logic inputs while the level at EN is high. When EN is low, the input data latch is not active; that is, data at the logic inputs will flow through the latch and immediately determine the state of the SLIC and drivers. Logic outputs NSTAT and NTSD are also latched. There is an internal pull-up associated with each of these logic outputs. The operation of EN with the logic outputs is slightly different from the operation of EN with the logic inputs. In order for valid data to be at the NSTAT and NTSD outputs, both the internal detector (i.e., an off-hook or thermal shutdown condition, respectively, exists) and pin EN must be low. Table 24 explains this.
dc Applications (continued)
Latched Parallel Data Interface
The L8567 uses a latched parallel data control scheme for both logic inputs and logic outputs. There is a latch enable (EN) pin associated with this control scheme. This data control scheme is designed to work in conjunction with the quad T7507 codec. The T7507 codec uses a serial data interface to receive and pass control information to and from the controlling processor. The T7507 controls the state of the L8567 SLIC via data inputs and outputs corresponding to those of the L8567 SLIC. The T7507 also provides the EN control signal. The T7507 is a quad codec; that is, four channels in a single package. Each quad codec is designed to control the four corresponding L8567 SLIC devices. Control inputs and outputs for the four channels are shared among the four SLICs. For example, there is only one B0 data output from the codec, and this control signal is passed to the B0 control input on the four associated SLICs. There are four EN outputs from the codec, one to each SLIC. Data on the shared input or output leads are valid to or from a given SLIC, depending on the state of EN pin associated with the individual SLIC. This is shown in Figure 29 below. The control data inputs to the SLIC are B0 and B1, which set the state of the SLIC and RD1I, RD2I, and RD3I, which control the state of the EMR drivers. If an
EN L8567-0 B0 NSTAT
ENABLE DATA INPUT DATA OUTPUT
EN L8567-1 B0 NSTAT
EN L8567-2 B0 NSTAT EN0 EN1 EN2 EN L8567-3 B0 NSTAT B0C NSTATc
12-3457(F)
D0 D1 T7507 CSEL CCLK
DATA OUT DATA IN CHIP SELECT CLOCK
SERIAL DATA INTERFACE TO CONTROLLER
EN3
Figure 29. Simplified Control Scheme Lucent Technologies Inc. 37
L8567 SLIC for People's Republic of China Applications
Data Sheet August 1999
Finally, the hybrid balance network cancels the unwanted amount of the receive signal that appears at the transmit port.
dc Applications (continued)
Latched Parallel Data Interface (continued)
Table 24. Valid Data at NSTAT and NTSD EN State 0 Off-hook--loop closure or ring trip 0 On-hook 1 Don't care EN State 0 Device in thermal shutdown 0 Normal operation--device state determined by B0, B1, and RD1 inputs 1 Don't care NSTAT 0 1 1 NTSD 0 1 1
First-Generation Codecs
These perform the basic filtering, A/D (transmit), D/A (receive), and -law/A-law companding. They all have an op amp in front of the A/D converter for transmit gain setting and hybrid balance (cancellation at the summing node). Depending on the type, some have differential analog input stages, differential analog output stages, and -law/A-law selectability. This generation of codecs is lower cost compared to second- and third-generation codecs, but needs the most complicated interface between the SLIC and codec. These codecs are most suitable for applications with fixed gains, termination impedance, and hybrid balance.
A simplified logic output latches schematic is shown in Figure 30.
Second-Generation Codecs
NRDET NSTAT CONTROL NLC INTERNAL LOOP CLOSURE DETECTORS
This class of devices includes a microprocessor interface for software control of the gains and hybrid balance. The hybrid balance is included in the device. ac programmability adds application flexibility and saves several passive components and also adds several I/O latches that are needed in the application. However, there is no transmit op amp, since the transmit gain and hybrid balance are set internally.
EN
12-3455(F)
Third-Generation Codecs
This class of devices includes the gains, termination impedance, and hybrid balance--all under microprocessor control. Depending on the device, it may or may not include latches. This generation of codec offers a very simple SLIC-codec interface with a minimal number of external components.
Figure 30. Logic Output Latches Like NSTAT, output NLED also reflects loop closure and ring trip status. Output NLED is not latched. This output is an open-collector output with sufficient drive capability to drive an LED. Multiple NLED can be connected to a common LED. NLED is valid regardless of the state of EN. NLED can be used as an unlatched alternative to NSTAT for control logic.
T7507 Codec
The T7507 provides third-generation codec functionality without the programmability. In the T7507, ac gain, termination impedance, and the hybrid balance network are set digitally; thus, the SLIC-codec interface requires virtually no external components. However, because all the ac parameters are fixed (and set for requirements in the PRC), the device is an extremely cost-effective solution.
ac Design
There are four key ac design parameters. Termination impedance is the impedance looking into the 2-wire port of the line card. It is set to match the impedance of the telephone loop in order to minimize echo return to the telephone set. Transmit gain is measured from the 2-wire port to the PCM highway, while receive gain is done from the PCM highway to the transmit port. 38
Lucent Technologies Inc.
Data Sheet August 1999
L8567 SLIC for People's Republic of China Applications
Outline Diagrams
32-Pin PLCC
Dimensions shown are metric. Note: The dimensions in this outline diagram are intended for informational purposes only. For detailed schematics to assist your design efforts, please contact your Lucent Technologies Sales Representative.
12.446 0.127 11.430 0.076 PIN #1 IDENTIFIER ZONE 1 30
4
5
29
13.970 0.076 14.986 0.127
13
21
14
20
3.175/3.556 SEATING PLANE 0.10
1.27 TYP
0.38 MIN TYP 0.330/0.533
5-3813 (F)r01
Lucent Technologies Inc.
39
L8567 SLIC for People's Republic of China Applications
Data Sheet August 1999
Outline Diagrams (continued)
44-Pin PLCC
Dimensions shown are metric. Note: The dimensions in this outline diagram are intended for informational purposes only. For detailed schematics to assist your design efforts, please contact your Lucent Technologies Sales Representative.
17.65 MAX 16.66 MAX PIN #1 IDENTIFIER ZONE
6
1
40
7
39
16.66 MAX 17.65 MAX
17
29
18
28
4.57 MAX SEATING PLANE 1.27 TYP 0.53 MAX 0.51 MIN TYP 0.10
5-2506 (F) r07
40
Lucent Technologies Inc.
Data Sheet August 1999
L8567 SLIC for People's Republic of China Applications
Ordering Information
Device Part No. LUCL8567AAU-D LUCL8567AAU-DT LUCL8567AP-D LUCL8567AP-DT Description PRC SLIC PRC SLIC PRC SLIC PRC SLIC Package 32-Pin PLCC (Dry-bagged, Tube) 32-Pin PLCC (Dry-bagged, Tape and Reel) 44-Pin PLCC (Dry-bagged, Tube) 44-Pin PLCC (Dry-bagged, Tape and Reel) Comcode 107891236 107891244 107957706 107957714
Lucent Technologies Inc.
41
For additional information, contact your Microelectronics Group Account Manager or the following: INTERNET: http://www.lucent.com/micro E-MAIL: docmaster@micro.lucent.com N. AMERICA: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHINA: Microelectronics Group, Lucent Technologies (China) Co., Ltd., A-F2, 23/F, Zao Fong Universe Building, 1800 Zhong Shan Xi Road, Shanghai 200233 P R. China Tel. (86) 21 6440 0468, ext. 316, FAX (86) 21 6440 0652 . JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148 Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 4354 2800 (Helsinki), ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid)
Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information.
Copyright (c) 1999 Lucent Technologies Inc. All Rights Reserved
August 1999 DS99-100ALC (Replaces DS98-001ALC)

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